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| DS1232LP/LPS DS1232LP/LPS Low Power MicroMonitor Chip FEATURES PIN ASSIGNMENT NC PBRST TD TOL 1 2 3 4 8 7 6 5 VCC ST RST RST PBRST NC TD NC TOL NC DS1232LP 8-Pin DIP (300 Mil) See Mech. Drawings Section GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC VCC NC ST NC RST NC RST * Super low-power version of DS1232 * 50 mA quiescent current * Halts and restarts an out-of-control microprocessor * Automatically failure restarts microprocessor after power GND * Monitors pushbutton for external override * Accurate 5% monitoring or 10% microprocessor power supply DS1232LPS 16-Pin SOIC (300 Mil) See Mech. Drawings Section PBRST TD TOL GND 1 2 3 4 8 7 6 5 VCC ST RST RST * 8-pin DIP, 8-pin SOIC or space saving -SOP package available * Optional 16-pin SOIC package available * Industrial temperature -40C to +85C available, designated N PBRST TD TOL GND 1 2 3 4 8 7 6 5 VCC ST RST RST DS1232LP (118 MIL -SOP) See Mech. Drawings Section DS1232LPS-2 8-Pin SOIC (150 Mil) See Mech. Drawings Section PIN DESCRIPTION PBRST TD TOL GND RST RST ST VCC - - - - - - - - Pushbutton Reset Input Time Delay Set Selects 5% or 10% VCC Detect Ground Reset Output (Active High) Reset Output (Active Low, open drain) Strobe Input +5 Volt Power DESCRIPTION The DS1232LP/LPS Low Power MicroMonitor Chip monitors three vital conditions for a microprocessor: power supply, software execution, and external override. First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance condition occurs, an internal power fail signal is generated which forces reset to the active state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of 250 ms to allow the power supply and processor to stabilize. The second function the DS1232LP/LPS performs is pushbutton reset control. The DS1232LP/LPS debounces the pushbutton input and guarantees an active reset pulse width of 250 ms minimum. The third function is a watchdog timer. The DS1232LP/LPS has an internal timer that forces the reset signals to the active state if 062698 1/7 DS1232LP/LPS the strobe input is not driven low prior to time-out. The watchdog timer function can be set to operate on timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds. signals of at least 250 ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is released from low level. OPERATION - WATCHDOG TIMER OPERATION - POWER MONITOR The DS1232LP/LPS detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When VCC falls below a preset level as defined by TOL, the VCC comparator outputs the signals RST and RST. When TOL is connected to ground, the RST and RST signals become active as VCC falls below 4.75 volts. When TOL is connected to VCC, the RST and RST signals become active as VCC falls below 4.5 volts. The RST and RST are excellent control signals for a microprocessor, as processing is stopped at the last possible moments of valid VCC. On power-up, RST and RST are kept active for a minimum of 250 ms to allow the power supply and processor to stabilize. The watchdog timer function forces RST and RST signals to the active state when the ST input is not stimulated for a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to VCC. The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive. If a high-to-low transition occurs on the ST input pin prior to time-out, the watchdog timer is reset and begins to time-out again. If the watchdog timer is allowed to time-out, then the RST and RST signals are driven to the active state for 250 ms minimum. The ST input can be derived from microprocessor address signals, data signals, and/or control signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to time-out. To guarantee that the watchdog timer does not time-out, a high-to- low transition must occur at or less than the minimum shown in Table 1. A typical circuit example is shown in Figure 2. OPERATION - PUSHBUTTON RESET The DS1232LP/LPS provides an input pin for direct connection to a pushbutton (Figure 1). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that RST and RST MICROMONITOR BLOCK DIAGRAM ST RST VCC TOL VCC TOLERANCE BIAS + - DIGITAL SAMPLER DIGITAL DELAY RST T.C. REFERENCE PBRST LEVEL SENSE AND DEBOUNCE TIME-OUT COMPARATOR TD VOLTAGE SENSE 062698 2/7 DS1232LP/LPS PUSHBUTTON RESET Figure 1 +5 VDC PBRST VCC +5 VDC TD TOL GND ST DS1232 LP/LPS RST RST ALE RST 8051 mP WATCHDOG TIMER Figure 2 +5 VDC PBRST VCC ST TD TOL GND DS1232 LP/LPS MREQ RST 10K Z80 RST ADDRESS BUS DECODER RST 062698 3/7 DS1232LP/LPS TIMING DIAGRAM: PUSHBUTTON RESET Figure 3 tPDLY PBRST tPB VIH VIL tRST RST VOH RST VOL TIMING DIAGRAM: STROBE INPUT Figure 4 INVALID STROBE ST MIN. tTD RST VALID STROBE INDETERMINATE STROBE MAX. WATCHDOG TIME-OUTS Table 1 TIME-OUT TD GND Float VCC MIN 62.5 ms 250 ms 500 ms TYP 150 ms 600 ms 1200 ms MAX 250 ms 1000 ms 2000 ms 062698 4/7 DS1232LP/LPS TIMING DIAGRAM: POWER DOWN Figure 5 tF VCC 4.75V VCCTP 4.25V RST tRPD VOH RST VOL TIMING DIAGRAM: POWER UP Figure 6 tR 4.75V 4.25V VCCTP VCC tRPU RST VOH RST VOL 062698 5/7 DS1232LP/LPS ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Pin Relative to Ground Voltage on I/O Relative to Ground Operating Temperature Operating Temperature (Industrial Version) Storage Temperature Soldering Temperature -0.5V to +7.0V -0.5V to VCC + 0.5V 0C to 70C -40C to +85C -55C to +125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Supply Voltage ST and PBRST Input High Level ST and PBRST Input Low Level SYMBOL VCC VIH VIL MIN 4.5 2.0 -0.3 TYP 5.0 MAX 5.5 VCC+0.3 +0.8 UNITS V V V (0C to 70C) NOTES 1 1 1 DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Output Current @ 2.4V Output Current @ 0.4V Low Level @ RST Output Voltage @ -500 uA Operating Current (CMOS) Operating Current (TTL) VCC Trip Point (TOL = GND) VCC Trip Point (TOL = VCC) SYMBOL IIL IOH IOL VOL VOH ICC1 ICC2 VCCTP VCCTP 4.50 4.25 200 4.62 4.37 VCC -0.5V VCC -0.1V MIN -1.0 -8 10 -10 TYP (0C to 70C; VCC = 4.5 to 5.5V) MAX +1.0 UNITS A mA mA 0.4 V V 50 500 4.74 4.49 A A V V 1 1, 7 2 8 1 1 NOTES 3 5 CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 7 UNITS pF pF (tA = 25C) NOTES 062698 6/7 DS1232LP/LPS AC ELECTRICAL CHARACTERISTICS PARAMETER PBRST = VIL RESET Active Time ST Pulse Width VCC Fail Detect to RST and RST VCC Slew Rate 4.75V to 4.25V VCC Detect to RST and RST Inactive VCC Slew Rate 4.25V to 4.75V PBRST Stable Low to RST and RST SYMBOL tPB tRST tST tRPD tF tRPU tR tPDLY 300 250 0 610 MIN 20 250 20 50 610 TYP (0C to 70C; VCC = 5V + 10%) MAX UNITS ms 1000 ms ns 175 s s 1000 ms ns 20 ms 4 6, 9 NOTES NOTES: 1. All voltages referenced to ground. 2. Measured with outputs open and ST and PBRST within 0.5V of supply rails. 3. PBRST is internally pulled up to VCC with an internal impedance of 40K typical. 4. tR = 5 s. 5. RST is an open drain output. 6. Must not exceed tTD minimum. See Table 1. 7. RST remains within 0.5V of VCC on power-down until VCC drops below 2.0V. RST remains within 0.5V of GND on power-down until VCC drops below 2.0V. 8. Measured with outputs open and ST and PBRST at TTL levels. 9. Watchdog can not be disabled. It must be strobed to avoid resets. MARKING INFORMATION: 8-pin DIP - "DS1232L" 16-pin SOIC - "DS1232L" 8-pin SOIC - "DS1232L" 8-pin -SOP - "1232" 062698 7/7 |
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